expert required who is good in ARMv8 Processor (digital logic design ) quartus prime software will be used in this project please check below attachment for project details and if you are good inbox

EECE 343 Project 3 Fall 2020

Project 3: Multi-cycle ARMv8 Processor

Prof. Kredo

Due by 23:59 November 1

Introduction

Objectives

• Implement a multi-cycle ARMv8 processor in SystemVerilog
• Integrate multiple modules from previous assignments
• Verify system operation using a testbench

Description

In this project you will build a multi-cycle ARMv8 processor in SystemVerilog, which will give you practice in
implementing large digital systems and strengthen your knowledge of computer architectures. The processor
must be able to execute all instructions listed in the Instruction Summary handout.

You created several of the components for your processor in previous assignments. The files below are
necessary or very helpful in completing the assignment. If any of these implementations do not work, fix
them first and get help soon. You will need to copy these files into your project directory.

• code checker.sv — from Activity 2
• classifier.sv — from Activity 7
• mc arm control.sv — from Activity 10
• alu.sv — from Project 1

You may find it helpful to start with mc addsub.sv from Activity 9, if it works correctly, and extend the
datapath to include other required elements.

Activity 10 has you implement the controlpath for your processor. Your primary effort for this assignment
is to build the datapath for the processor and integrate all the components into one functioning system.
Figure 1 contains the datapath discussed in class, which you are to implement. All control signals are
highlighted in red. However, the figure is missing the small changes required to implement STR.
You will need to determine how to implement STR.

To get you started working on your datapath before Activity 10, the project contains a solution control-
path based on a ROM implementation. You can use this controlpath to verify the operation of your datapath
until you complete Activity 10. Once you have a complete Activity 10, you should copy it into your project
and replace the blank starter file. To get full credit you must pass all tests using your datapath and your
controlpath. You may not implement your controlpath as a ROM.

EECE 343 Project 3 Fall 2020

Simulation

Several signals are provided as output from the processor to enable testing. Ensure these signals are connected
as indicated below.

Processor output signals:

PC, IR, DA, A, B, Imm, Flags : Current contents of the named register, where Flags=N,Z,C,V
Mem r, Mem w, RF w : Memory read and write control signals, Register File write control signal
MemWriteAddr : The 32-bit address (location) of memory to write; this value is ignored if Mem w is low
MemWriteData : The 32-bit value to write to memory; this value is ignored if Mem w is low
RFWriteAddr : The 5-bit register number to write; this value is ignored if RF w is low
RFWriteData : The 32-bit value to write to the register file; this value is ignored if RF w is low

Testing for this assignment will occur by using two testbenches, which are already setup in the provided
Quartus Prime project archive. The initial testbench, ‘ROM Control,’ uses the solution control unit based
on a ROM. The second testbench, ‘Student Control,’ uses your controlpath with your datapath. Use the
‘Student Control’ testbench once you have a complete and correct datapath. To get full credit your system
needs to pass the ‘Student Control’ testbench without errors. You run a new testbench by selecting a
different testbench in the project Simulation settings and then run an RTL Simulation, as you have done in
previous assignments.

Grading

Include all group member names in your source files and hand them in through Learn. Only one submission
per group.

Well organized and documented designs are easier to grade and thus tend to earn more points than poor
designs. If the grader can find a mistake quickly, then you’ll get partial credit. However, this is harder to
do if the grader can’t determine what you were doing.

Every student is strongly encouraged to complete an independent Group Evaluation form on Learn for
each project, which helps ensure all students participate equally. Do this even if you work alone.

The project will be graded based on the following point distribution. Partial credit may be given as
appropriate.

• 15 points: Arithmetic instructions (ADDS, ADD, SUBS, SUB)
• 15 points: Logical instructions (AND, ORR, EOR, ANDS)
• 10 points: Shift instructions (LSL, LSR, ASR, ROR)
• 15 points: Memory instructions (LDR, STR)
• 10 points: Unconditional branch instructions (B)
• 15 points: Conditional branch instructions (B.COND for the conditions in the Instruction Summary)
• 20 points: Datapath correct with student controlpath

You are strongly encouraged to implement and test your system in the order listed above. Later tests
depend upon earlier tests. For example, you are highly unlikely to pass memory tests without arithmetic
instructions working correctly.
Submit your mc arm.sv mc arm control.sv files through Blackboard Learn.

Hints

• Test and debug in steps. Start with a subset of the project requirements, implement it, test it, and
then add other requirements. Performing the testing and debugging in steps will ease your efforts. For
example, you could implement the logic operations, then include the arithmetic operations, and finally
the shift operations.

• Think about the hardware you are creating before writing any SystemVerilog. At this point in the
class, you should start with a concrete picture of the hardware you want to create.

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Figure 1: Multi-Cycle ARMv8 Processor (without STR)